diagnostic scan register cy29fct818t sccs012 - may 1994 - revised february 2000 data sheet acquired from cypress semiconductor corporation. data sheet modi?ed to remove devices not offered. copyright ? 2000, texas instruments incorporated features ? function, pinout and drive compatible with fct, f logic and am29818 ? fct-c speed at 6.0 ns max. (coml), fct-a speed at 12.0 ns max. (mil) ? reduced v oh (typically = 3.3v) versions of equivalent fct functions ? edge-rate control circuitry for signi?cantly improved noise characteristics ? power-off disable feature ? matched rise and fall times ? fully compatible with ttl input and output logic levels ? sink current 64 ma (coml), 20 ma (mil) source current 32 ma (coml), 3 ma (mil) ? 8-bit pipeline and shadow register ? esd > 2000v functional description the fct818t contains a high-speed 8-bit general-purpose data pipeline register and a high-speed 8-bit shadow register. the general-purpose register can be used in an 8-bit wide data path for a normal system application. the shadow regis- ter is designed for applications, such as diagnostics in sequen- tial circuits, where it is desirable to load known data at a spe- ci?c location in the circuit and to read the data at that location. the shadow registers can load data from the output of the fct818t, and can be used as a right-shift register with bit-serial input sdi and output sdo, using dclk. the data register input is multiplexed to enable loading from the shadow register or from the data input pins using pclk. note that data can be loaded simultaneously from the shadow register to the pipeline register, and from the pipeline register to the shadow register provided set-up and hold time requirements are satis?ed with respect to the two independent clock inputs. in a typical application, the general-purpose register in the fct818t replaces an 8-bit data register in the normal data path of a system. the shadow register is placed in an auxiliary bit-serial loop which is used for diagnostics. during diagnostic operation, data is shifted serially into the shadow register, then transferred to the general purpose register to load a known value into the data path. to read the contents at that point in the data path, the data is transferred from the data register into the shadow register, then shifted serially in the auxiliary diagnostic loop to make it accessible to the diagnostics controller. this data is then compared with the expected value to diagnose faulty operation of the sequential circuit. the outputs are designed with a power-off disable feature to allow for live insertion of boards. logic block diagram pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 oe dclk d 1 d 2 d 3 d 4 d 5 d 0 d 6 d 7 sdi gnd v cc mode sdo y 0 y 1 y 3 y 4 y 5 y 7 y 6 15 y 2 top view 28 4 3 2 1 27 2021 222324 26 19 d 5 d 4 y 2 y 5 25 y 1 y 7 d 7 sdi d 0 nc nc dclk oe mode y 0 gnd nc nc y 4 d 2 lcc top view y 3 v cc 5 6 7 8 9 10 11 d 1 d 3 12 13 14 15 16 17 18 d 6 pclk y 6 sdo pclk dip, soic, qsop 8-bit shadow register clk d q mux 8-bit pipeline register oe pclk mode dclk sdi sdo d 0 - d 7 p 0 - p 7 y 0 - y 7 8 8 8 8 s 0 - s 7
cy29fct818t 2 maximum ratings [2, 3] (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature .................................C65 c to +150 c ambient temperature with power applied .............................................C65 c to +135 c supply voltage to ground potential ............... C0.5v to +7.0v dc input voltage............................................ C0.5v to +7.0v dc output voltage ......................................... C0.5v to +7.0v dc output current (maximum sink current/pin).......120 ma power dissipation .......................................................... 0.5w static discharge voltage............................................>2001v (per mil-std-883, method 3015) function table [1] inputs inputs shadow register pipeline register operation mode sdi dclk pclk sdo l l x x x x s 7 s 7 s 0 ? sdi s i ? s i-1 na na p i ? d i serial shift; d 7 Cd 0 output disabled load pipeline register from data input h h h l h x x x x l h sdi s i ? y i hold na na na p i ? s i load shadow register from y output hold shadow register; d 7 - d 0 output enabled load pipeline register from shadow register operating range range range ambient temperature v cc commercial all C40 c to +85 c 5v 5% military [4] all C55 c to +125 c 5v 10% electrical characteristics over the operating range parameter description test conditions min. typ. [5] max. unit v oh output high voltage v cc =min., i oh =C32 ma coml 2.0 v v cc =min., i oh =C15 ma coml 2.4 3.3 v v cc =min., i oh =C3 ma mil 2.4 3.3 v v ol output low voltage v cc =min., i ol =64 ma coml 0.3 0.55 v v cc =min., i ol =20 ma mil 0.3 0.55 v v ih input high voltage 2.0 v v il input low voltage 0.8 v v h hysteresis [6] all inputs 0.2 v v ik input clamp diode voltage v cc =min., i in =C18 ma C0.7 C1.2 v i i input high current v cc =max., v in =v cc 5 m a i ih input high current v cc =max., v in =2.7v 1 m a i il input low current v cc =max., v in =0.5v 1 m a i ozh off state high-level output current v cc =max., v out =2.7v 10 m a i ozl off state low-level output current v cc =max., v out =0.5v C10 m a i os output short circuit current [7] v cc =max., v out =0.0v C60 C120 C225 ma i off power-off disable v cc =0v, v out =4.5v 1 m a
cy29fct818t 3 document #: 38-00275-b notes: 1. na = not applicable 2. unless otherwise noted, these limits are over the operating free-air temperature range. 3. unused inputs must always be connected to an appropriate logic voltage level, preferably either v cc or ground. 4. t a is the instant on case temperature. 5. typical values are at v cc =5.0v, t a =+25?c ambient. 6. this parameter is speci?ed but not tested. 7. not more than one output should be shorted at a time. duration of short should not exceed one second. the use of high-speed test apparatus and/or sampl e and hold techniques are preferable in order to minimize internal chip heating and more accurately re?ect operational values. otherwise prolonged sh orting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameters tests. in any sequence of paramet er tests, i os tests should be performed last. electrical characteristics over the operating range parameter description test conditions min. typ. [5] max. unit capacitance [8] parameter description test conditions typ. [5] max. unit c in input capacitance 5 10 pf c out output capacitance 9 12 pf power supply characteristics parameter description test conditions typ. [5] max. unit i cc quiescent power supply current v cc =max., v in < 0.2v, v in > v cc C0.2v 0.2 1.5 ma d i cc quiescent power supply current (ttl inputs high) v cc =max., v in =3.4v, f 1 =0, outputs open [8] 0.5 2.0 ma i ccd dynamic power supply current [9] v cc =max., 50% duty cycle, outputs open, one input toggling, oe=gnd, v in < 0.2v or v in > v cc C0.2v 0.25 ma/mhz i c total power supply current [10] v cc =max., 50% duty cycle, outputs open, f 0 =10 mhz, one bit toggling at f 1 =5 mhz, oe=gnd, v in < 0.2v or v in > v cc C0.2v 5.3 ma v cc =max., 50% duty cycle, outputs open, f 0 =10 mhz, one bit toggling at f 1 =5 mhz, oe=gnd, v in =3.4v or v in =gnd 7.3 ma v cc =max., 50% duty cycle, outputs open, f 0 =10 mhz, eight bits and four controls toggling, f 1 =5 mhz, oe=gnd, v in < 0.2v or v in > v cc C0.2v 17.8 [11] ma v cc =max., 50% duty cycle, outputs open, f 0 =10 mhz, eight bits and four controls toggling, f 1 =5 mhz, oe=gnd, v in =3.4v or v in =gnd 30.8 [11] ma notes: 8. per ttl driven input (v in =3.4v); all other inputs at v cc or gnd. 9. this parameter is not directly testable, but is derived for use in total power supply calculations. 10. i c =i quiescent + i inputs + i dynamic i c =i cc + d i cc d h n t +i ccd (f 0 /2 + f 1 n 1 ) i cc = quiescent current with cmos input levels d i cc = power supply current for a ttl high input (v in =3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f 0 = clock frequency for registered devices, otherwise zero f 1 = input signal frequency n 1 = number of inputs changing at f 1 all currents are in milliamps and all frequencies are in megahertz. 11. values for these conditions are examples of the i cc formula. these limits are speci?ed but not tested.
cy29fct818t 4 switching characteristics over the operating range [12] parameter description fct818at fct818ct unit fig. no. [13] military commercial min. max. min. max. t pd propagation delay pclk to y mode to sdo sdi to sdo dclk to sdo 12 18 18 30 6.0 7.2 7.1 7.2 ns ns ns ns 5 6 3 5 t s set-up time d to pclk mode to pclk y to dclk mode to dclk sdi to dclk dclk to pclk pclk to dclk 6 15 5 12 10 15 45 2.0 3.5 2.0 3.5 3.5 3.5 8.5 ns ns ns ns ns ns ns 4 t h hold time d to pclk mode to pclk y to dclk mode to dclk sdi to dclk 2 0 5 5 0 1.5 0 1.5 1.5 0 ns ns ns ns ns 4 t plz output disable time low oe to y dclk to d 20 45 5.5 5.5 ns ns 7 5 t phz output disable time high oe to y dclk to d 30 90 8.0 8.0 ns ns 8 5 t pzl output enable time low oe to y dclk to d 20 35 8.0 9.0 ns ns 7 5 t pzh output enable time high oe to y dclk to d 20 30 8.5 9.0 ns ns 8 5 t w pulse width pclk (high and low) dclk (high and low) 15 25 5.0 5.0 ns ns 5 5 speed (ns) ordering code package name package type operating range 6.0 CY29FCT818CTPC p13/13a 24-lead (300-mil) molded dip commercial cy29fct818ctqct q13 24-lead (150-mil) qsop cy29fct818ctsoc/soct s13 24-lead (300-mil) molded soic 12.0 cy29fct818atdmb d14 24-lead (300-mil) cerdip military notes: 12. minimum limits are speci?ed but not tested on propagation delays. 13. see parameter measurement information in the general information section.
cy29fct818t 5 package diagrams 24-lead (300-mil) cerdip d14 mil-std-1835 d- 9 config.a 28-square leadless chip carrier l64 mil-std-1835 c-4 24-lead (300-mil) molded dip p13/p13a
cy29fct818t 6 package diagrams (continued) 24-lead quarter size outline q13 24-lead (300-mil) molded soic s13
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